Electroplating on ultra-thin seed layers

ABSTRACT

Methods and structures for the electroplating on ultra-thin seed layers are disclosed. A dual layer structure is utilized, consisting of a thicker, highly conductive layer surrounding device structures. Within the device die, an ultra-thin seed layer is employed, which is electrically coupled to the conduction layer. Using this technique, electroplating of critical device structures can be carefully controlled and made uniform across the full diameter of the wafer. The technique also allow for the deployment of ultra-thin seed layers of varying thickness and composition in different locations within the circuit device, or in different die on the wafer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending non-provisionalapplication Ser. No. 11/645,397 filed Dec. 26, 2006 entitledELECTROPLATING ON ULTRA-THIN SEED LAYERS, and claims benefit thereof.The aforementioned application is herein incorporated by reference inits entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to structures and methods for electroplating onseed layers. More specifically, the invention relates to structures andmethods for electroplating on ultra-thin seed layers.

2. Description of the Related Art

The use of seed layers to electroplate conductive interconnect lines andmagnetic shield structures is widely practiced in the art of integratedcircuit and micro-circuit fabrication. Typically, a thin, electricallyconductive (seed) layer is vapor deposited on the circuit structure,which subsequently acts as a starting cathode for the electrochemicaldeposition of a much thicker plated layer. This technique is useful fordepositing thicker metal layers used for interconnect, which would takevery long times if deposited from the vapor by CVD or sputtering, or fordepositing copper which is easily and economically electroplated.

A serious problem experienced by practitioners electroplating on seedlayers results from the relatively low conductivity of thin seed layersas the wafer size increases and seed layer thickness decreases,resulting in significant voltage drops across the wafer during theelectroplating process. Typically, electrical contact with the wafer inthe plating tools occurs near the outer edge (or perimeter) of thewafer, and electrical current needed for the deposition of plated metalin the center of the wafer must travel across the radius. As wafer sizescontinue to increase, and seed layers continue to decrease in thickness,this problem is exacerbated to the point where poor plating uniformityresults. In some cases, there may even be a lack of plated conductor inthe center portions of the wafer.

One solution to this problem is disclosed in FIGS. 1 a, 1 b, 2 a, 2 b,and 3 a, 3 b, of the prior art. FIG. 1 a (Prior Art) is a schematic planview of a wafer substrate 102 having a plurality of device die 104 a-104f, containing previously fabricated device structures (not shown). FIG.1 b (Prior Art) is a cross sectional view through section A-A of FIG. 1a. A single seed layer is then blanket deposited on the wafer surface inpreparation for the electroplating process. FIG. 2 a (Prior Art) is aschematic plan view of the wafer of FIG. 1 a subsequent to thedeposition of a seed layer 202. Subsequent to the seed layer deposition,a conduction layer, typically copper, is electroplated in the outerperimeter areas of the wafer and in the “galley” areas between devicedie. Generally, no plating is performed within the device areas of thedie, as these areas are masked off. FIG. 3 a (Prior Art) is a plan viewof the wafer of FIG. 2 a subsequent to the electroplating of aconductive layer 306. Layer 306 serves as a conductive plating “buss”for subsequent plating of device structures within the die (i.e. 104a-104 f). In the plating tools, contact with the wafer is typically madeat the outer perimeter areas of the wafer, for example in area 302. Thedark arrows 304 show the current paths that result during the subsequentplating of structures within the device die. Although this techniquedoes reduce voltage drops across the wafer when plating devicestructures, it has a number of disadvantages.

One disadvantage is that the seed layer 202 still must be reasonablythick, typically 250 to 1000 angstroms or greater. Otherwiseelectroplating of the conduction layer 306 will be non-uniform, withlarge variations in plated thickness occurring from center to edge.Voids may also be formed in the galleys, causing some die areas to beisolated in subsequent device structure plating processes. The use ofultra-thin seed layers, for example seed layers under 250 angstroms, maybe unsuitable for this process.

Another disadvantage is that this prior art process uses a single seedlayer of uniform composition. In current and future device technology,multiple seed layers of different chemical compositions, layerstructures, and thickness may be required within the device die atvarying locations. This functionality is required because seed layershave additional functional properties that are customized to matchparticular device structures. For example, seed layers may be requiredto have anti-reflective properties to aid in photo resist exposure. Theymust also have good adhesion to both underlying materials and photoresists that will be deposited on their surface, as well as the platedmaterials that will be deposited on them. They need to be compatiblewith the plating bath chemistry, and not oxidize, corrode, or dissolvein the bath. They need to be compatible with the plated device design,if they are part of critically dimensioned structure like aperpendicular write head, for example. A single seed layer cannot meetall these requirements. Thicker seed layers suitable for the prior artprocess, may not be compatible with device structures such asperpendicular write heads, where the seed layer is an integral part ofthe structure separating the plated shield from other structures withinthe head. Furthermore, due to the wide variety of seed materials needed,some compositions may not be chemically stable when exposed to copperplating bath chemistries, particularly at thickness ranges below 250angstroms.

What is needed is a better process for electroplating on ultra-thin seedlayers of varying composition and thickness, while maintaining gooddevice structure plating uniformity across the full diameter of thewafer.

A summary of the relevant prior art is provided below.

An article entitled “Network Plating on Seed Layer to Improve PlatingUniformity”, by Fu et al., published in the IBM Technical DisclosureBulletin, May 1992, discloses a method to improve plating uniformitythroughout the' active device area of a substrate based on pre-platingthe inactive area of a substrate to enhance electrical conductivity andcurrent distribution across the substrate.

United States Patent Application Publication 2001/0022704 discloses amethod and system for a write head. The method and system include thesteps of providing a first pole and providing a bottom antireflectivecoating (BARC) layer. The BARC layer is conductive, nonmagnetic, and anantireflective coating. A portion of the BARC layer is disposed abovethe first pole. The method and system also include providing aphotoresist structure having a trench therein. The method and systemalso include providing a second pole. A portion of the second pole isdisposed above the portion of the BARC layer and within the trench.Thus, the width of the pole may be better controlled.

U.S. Pat. No. 5,744,019 discloses multiple-layer thin film devicesdeposited by electroplating on an otherwise substantially cleansubstrate wafer. The composition of the electroplated alloy layers ismaintained substantially uniform using a cathode assembly on which thesubstrate wafer is mounted. The cathode assembly includes an innercathode ring electrically connected to the wafer, a thief ring externalto the cathode ring and an insulating ring connected between andelectrically insulating the cathode and thief rings. The cathode ringand the thief ring are powered by separate power sources.

U.S. Pat. No. 5,805,392 discloses pole pieces of a thin film head formedby two thin film layers of the magnetic metal NiFe, each NiFe layerbeing about 20,000 angstroms thick. These two NiFe layers are separatedby an electrically insulating layer of alumina (Al₂O₃), ceramic or NiFeoxide that is about 100 angstroms thick. In one embodiment, a hard-bakedphotoresist layer is formed only around the edges of the first NiFelayer, the electrically insulating layer is deposited over the topsurface of the first NiFe layer and over the hard-baked photoresistlayer, and the second NiFe layer is then deposited, thus providing athree-layer metal/insulator/metal pole piece wherein the hard bakedphotoresist blocks edge short circuiting between the two thin film NiFelayers. In another embodiment, edge short circuiting is minimized byallowing a small filament(s) of a high electrical resistance platingseed layer of NiFe to extend between the two NiFe thin film layers, thehigh resistance of these long and thin NiFe filaments being much greaterthan the resistance of the two NiFe thin film layers.

U.S. Pat. No. 5,901,432 discloses a method for making a merged thin filmread/write head, where the first pole piece includes a pedestal or poletip portion that extends up from the first pole piece layer, usingelectroplating to form the gap so that the gap layer does not have to beremoved later. After the first pole piece is deposited, the coilinsulation structure is built over the first pole piece. Afterwards anelectrically conductive seed layer of the same ferromagnetic material asthe first pole piece is formed over the wafer to provide an electricallyconductive path for subsequent electroplating. After the seed layerdeposition, a photoresist pattern is then formed to define the shape ofthe second pole piece. Nonmagnetic nickel-phosphorous is thenelectroplated onto the seed layer in the region not covered by thephotoresist pattern to form the gap layer. The second ferromagneticlayer is then electroplated onto the gap layer to define the shape ofthe second pole piece. The thickness of the second pole piece layer isdeliberately made thicker than the desired final thickness because thesecond pole piece layer is used as a mask for subsequent ion beammilling to form the notched pole tip element of the first pole piece.The photoresist is removed and ion beam milling performed to remove theseed layer and a portion of the first pole piece layer to define thepedestal pole tip element of the first pole piece. The ion beam millingdoes not have to remove the gap layer because the electroplated gap hasbeen defined by the photoresist pattern to have the desired trackwidth.

U.S. Pat. No. 6,140,234 discloses selectively plating recesses in asemiconductor structure, by providing electrical insulating layer overthe semiconductor substrate and in the recesses, followed by forming aconductive barrier over the insulating layer; providing a plating seedlayer over the barrier layer; depositing and patterning a photoresistlayer over the plating seed layer; planarizing the insulated horizontalportions by removing the horizontal portions of the seed layer betweenthe recesses; removing the photoresist remaining in the recesses; andthen electroplating the patterned seed layer with a conductive metalusing the barrier layer to carry the current during the electroplatingto thereby only plate on the seed layer. In an alternative process, abarrier film is deposited over recesses in an insulator. Then,relatively thick resists are lithographically defined on the fieldregions, on top of the barrier film over the recesses. A plating base orseed layer is deposited, so as to be continuous on the horizontalregions of the recesses in the insulator, but discontinuous on theirsurround wall. The recesses are then plated using the barrier filmwithout seed layers at the periphery of the substrate wafers forelectrical contact. After electroplating, the resist is removed bylift-off process and exposed barrier film is etched by RIE method or byCMP. Also provided is a semiconductor structure obtained by the aboveprocesses.

U.S. Pat. No. 6,514,393 discloses an electrochemical reactor used toelectrofill damascene architecture for integrated circuits or forelectropolishing magnetic disks. An inflatable bladder is used to screenthe applied field during electroplating operations to compensate forpotential drop along the radius of a wafer. The bladder establishes aninverse potential drop in the electrolytic fluid to overcome theresistance of a thin film seed layer of copper on the wafer.

U.S. Pat. No. 6,540,928 discloses a method and apparatus for fabricatingan electroplating mask for the formation of a miniature magnetic poletip structure. The method incorporates a silylation process to silylatephoto-resist after creating a photo-resist cavity or to trench in theelectroplating mask. The silylation process is performed after a dryetch of the photo-resist. Alternatively, silylation is performed after alithographic patterning of the trench. As a result of chemical biasing,the vertical side walls of the photoresist layer shift inward creating anarrower trench. The resulting structure formed after electroplating hasa width of less than 0.3 micrometers. This structure can be used as amagnetic pole of a thin film head (“TFH”) for a data storage device.

U.S. Pat. No. 6,589,816 discloses a method of forming metal connectionelements in integrated circuits formed on adjacent areas of a wafer,including forming a conductive seed layer on a substrate of the wafer. Afirst mask covers the integrated circuits and leaves exposed areas ofthe seed layer overlying predetermined scribe lines used for separationof the integrated circuits. Using the seed layer as a cathode, a metalis deposited by an electrochemical process on exposed areas of the seedlayer. The first mask is removed and a second mask is formed, leavingpredetermined areas of the seed layer exposed. Using the seed layer as acathode a metal is deposited on the exposed predetermined areas by anelectrochemical process. The second mask is then removed. Connectionelements of uniform thickness throughout the substrate are produced withthe use of a very thin seed layer.

U.S. Pat. No. 6,774,039 discloses copper bus bars formed betweenadjacent die on a wafer during the process flow. The bus bars arebetween 50 and 100 microns wide and between 2 and 5 microns deep. Abarrier layer is formed between the bus bars and the die to preventcopper diffusion. A dielectric layer is deposited over the bus bars anddie and etched with contacts and features, such as vias. A seed layer issubsequently deposited over the wafer, which allows electricalconductance between the bus bars and the die during a subsequentelectroplating process to fill the features and contacts. The bus barscarry electroplating current from the die edge to the die center. As aresult, current does not need to be carried by a low sheet resistivityseed layer from the wafer edge to the center. This allows the seed layerto be thinner and of materials other than copper. Further, thinner seedlayers allow thicker barrier layer for more reliability.

U.S. Pat. No. 6,807,027 discloses a perpendicular write head including amain pole, a return pole, and conductive coils. The main pole includes aseed layer and a magnetic layer that is plated upon the seed layer. Theseed layer is nonmagnetic, electrically conductive, andcorrosion-resistant. The return pole is separated from the main pole bya gap at an air bearing surface of the write head and is coupled to themain pole opposite the air bearing surface. The conductive coils arepositioned at least in part between the main pole and the return pole.

U.S. Pat. No. 6,811,670 discloses a method for forming electroplatingcathode contacts around the periphery of a semiconductor wafer,including forming an insulating layer over a conductive layer extendingat least around the periphery of a semiconductor wafer substrate;etching a plurality of openings around a peripheral portion of thesemiconductor wafer substrate through the insulating layer to extendthrough a thickness of the insulating layer in closed communication withthe conductive layer said conductive area in electrical communicationwith a central portion of the semiconductor wafer substrate; filling theplurality of openings with metal to form electrically conductivepathways; planarizing the electrically conductive pathway surfaces; and,forming a metal layer over the electrically conductive pathway surfacesto form a plurality of contact pads for contacting a cathode forcarrying out an electroplating process.

U.S. Pat. No. 6,861,355 discloses a seed film and methods incorporatingthe seed film in semiconductor applications. The seed film includes oneor more noble metal layers, where each layer of the one or more noblemetal layers is no greater than a mono-layer. The seed film alsoincludes either one or more conductive metal oxide layers or one or moresilicon oxide layers, where either layer is no greater than amono-layer. The seed film can be used in plating, includingelectroplating, conductive layers, over at least a portion of the seedfilm. Conductive layers formed with the seed film can be used infabricating an integrated circuit, including fabricating capacitorstructures in the integrated circuit.

U.S. Pat. No. 6,949,833 discloses a structure including a substrate witha top surface and a bottom surface, an etched dielectric layer havingsidewalls and an upper surface, wherein the etched dielectric layer witha thickness of v, is positioned upon a first portion of the top surfaceof the substrate but not positioned upon a second portion of the topsurface of the substrate having a width equal to x, an atomic layerdeposited (ALD) film with a thickness of y, positioned upon the uppersurface of the etched dielectric layer, the sidewalls of the etcheddielectric layer, and the second portion of the top surface of thesubstrate, and a trench formed by the atomic layer with a width equal tox−2y. The patent also discloses a method of forming a structure with atrench that includes the steps of depositing a dielectric layer on asubstrate, forming a patterned photoresist on the dielectric layer,forming a space having a width x, by etching the dielectric layer,removing the patterned photoresist to form a gap having sidewalls and abottom, and depositing an atomic layer with a thickness of y on theetched dielectric layer, and the sidewalls and the bottom of the gap,wherein a trench is formed by the atomic layer deposited on thesidewalls and bottom of the gap.

U.S. Pat. No. 7,037,574 discloses an atomic layer deposition (ALD)process that deposits thin films for microelectronic structures, such asadvanced gap and tunnel junction applications, by plasma annealing atvarying film thicknesses to obtain desired intrinsic film stress andbreakdown film strength. The primary advantage of the ALD process is thenear 100% step coverage with properties that are uniform alongsidewalls. The process provides smooth (R_(a) about 2 angstroms), pure(impurities<1 at. %), AlO_(x) films with improved breakdown strength(9-10 MV/cm) with a commercially feasible throughput.

U.S. Pat. No. 7,052,922 discloses a method and apparatus for platingfacilitating the plating of a small contact feature of a wafer die whileproviding a relatively stable plating bath. The method utilizes asupplemental plating structure that is larger than a die contact that isto be plated. The supplemental plating structure may be located on thewafer, and is conductively connected to the die contact. Conductiveconnection between the die contact and the supplemental platingstructure facilitates the plating of the die contact. The supplementalplating structure also can be used to probe test the die prior tosingulation.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method forelectroplating device structures, including vapor depositing a seedlayer on a first portion of a wafer surface; vapor depositing aconduction layer on a second portion of the wafer surface, wherein theconduction layer is electrically coupled to the seed layer; and,electroplating a device structure on the seed layer by conductingelectrical current through the conduction layer to the seed layer.

It is another object of the present invention to provide a method forelectroplating device structures, including vapor depositing a firstseed layer on a first portion of a wafer surface; vapor depositing asecond seed layer on a second portion of the wafer surface; vapordepositing a conduction layer on a third portion of the wafer surface,wherein the conduction layer is electrically coupled to the first andsecond seed layers; electroplating a first device structure on the firstseed layer by conducting electrical current through the conduction layerto the first seed layer; and, electroplating a second device structureon the second seed layer by conducting electrical current through theconduction layer to the second seed layer.

It is another object of the present invention to provide a method forelectroplating device structures, including vapor depositing a seedlayer on a wafer surface, vapor depositing a conduction layer on a firstportion of the seed layer and, electroplating a device structure on asecond portion of the seed layer by conducting electrical currentthrough the conduction layer to the second portion of the seed layer.

It is yet another object of the present invention to provide a methodfor electroplating device structures, including vapor depositing aconduction layer on a first portion of a wafer surface, vapor depositinga seed layer on a second portion of the wafer surface, and on at least aportion of said conduction layer; and, electroplating a device structureon the seed layer covering the second portion of the wafer surface, byconducting electrical current through the conduction layer to at least aportion of the seed layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood when consideration isgiven to the following detailed description thereof. Such descriptionmakes reference to the annexed drawings, wherein:

FIG. 1 a (Prior Art) is a schematic plan view of a wafer having aplurality of device die;

FIG. 1 b (Prior Art) is a cross sectional view through section A-A ofFIG. 1 a;

FIG. 2 a (Prior Art) is a schematic plan view of the wafer of FIG. 1 asubsequent to the deposition of seed layer 202;

FIG. 2 b (Prior Art) is a cross section view through section B-B of FIG.2 a;

FIG. 3 a (Prior Art) is a schematic plan view of the wafer of FIG. 2 asubsequent to the electroplating of a conduction layer 306;

FIG. 3 b (Prior Art) is a cross sectional view through section C-C ofFIG. 3 a;

FIG. 4 a is a schematic plan view of a wafer subsequent to thedeposition of ultra-thin seed layer 406, in accordance with anembodiment of the present invention;

FIG. 4 b is a cross sectional view through section D-D of FIG. 4 a, inaccordance with an embodiment of the present invention;

FIG. 4 c is an expanded schematic plan view of die 404 c of FIG. 4 a, inaccordance with an embodiment of the present invention;

FIG. 5 a is a schematic plan view of a wafer subsequent to the vapordeposition of conduction layer 502, in accordance with an embodiment ofthe present invention;

FIG. 5 b is a cross sectional view through section E-E of FIG. 5 a, inaccordance with an embodiment of the present invention;

FIG. 5 c is an expanded schematic plan view of die 404 c of FIG. 5 a, inaccordance with an embodiment of the present invention;

FIG. 6 a is a schematic plan view of a wafer subsequent to the vapordeposition of conduction layer 602, in accordance with an embodiment ofthe present invention;

FIG. 6 b is a cross sectional view through section F-F of FIG. 6 a, inaccordance with an embodiment of the present invention;

FIG. 6 c is an expanded schematic plan view of die 404 c of FIG. 6 a, inaccordance with an embodiment of the present invention;

FIG. 7 a is a schematic plan view of a wafer subsequent to the vapordeposition of ultra-thin seed layer 702, in accordance with anembodiment of the present invention;

FIG. 7 b is a cross sectional view through section G-G of FIG. 7 a, inaccordance with an embodiment of the present invention;

FIG. 7 c is an expanded schematic plan view of die 404 c of FIG. 7 a, inaccordance with an embodiment of the present invention;

FIG. 8 a is a schematic plan view of a wafer subsequent to the vapordeposition of conduction layer 804, and the selective vapor depositionof a plurality of ultra-thin seed layers, in accordance with anembodiment of the present invention;

FIG. 8 b is a cross sectional view through section H—H of FIG. 8 a, inaccordance with an embodiment of the present invention;

FIG. 8 c is an expanded schematic plan view of die 404 c of FIG. 8 a, inaccordance with an embodiment of the present invention;

FIG. 9 a is a schematic block diagram of a first electroplating process,in accordance with an embodiment of the present invention;

FIG. 9 b is a schematic block diagram of a second electroplatingprocess, in accordance with an embodiment of the present invention;

FIG. 9 c is a schematic block diagram of process step 902 of FIGS. 9 aand 9 b, in accordance with an embodiment of the present invention; and,

FIG. 9 d is a schematic block diagram of process step 904 of FIGS. 9 aand 9 b, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 a-3 b have been discussed above in the Background section.

FIG. 4 a is a schematic plan view 400 of a wafer subsequent to thedeposition of ultra-thin seed layer 406, in accordance with anembodiment of the present invention. FIG. 4 b is a cross sectional view401 through section D-D of FIG. 4 a. The dashed boxes in FIG. 4 arepresent regions of active device areas formed on wafer 402 surface,as, for example, shown in FIG. 1 a (Prior Art). For subsequentdiscussion, these areas will be referred to as device die. An exemplaryarray of device die is represented by items 404 a-404 f. Within thedevice die, numerous previously fabricated devices are present. Furtherprocessing steps may require that various device structures aresubsequently electroplated over these previously fabricated devices,which requires electroplating on localized areas of the device die. Theelectroplated device structures may be, for example, interconnect lines,vias, or magnetic shield structures. The device die are separated fromeach other by thin passages known as galleys. As mentioned previously,electroplating current must be delivered from the outer perimeter areasof the wafer, through the galleys, to the localized areas within thedevice die themselves. A first step in this process is represented byFIG. 4 a, wherein an ultra-thin seed layer 406 is deposited throughoutthe full wafer surface. An ultra-thin seed layer is typically a seedlayer less than about 25 nm (250 Angstroms) in thickness, and may be asthin as 1 nm (10 Angstroms). The ultra-thin seed layer is generallycomprised of a metal or metal alloy, preferably: a noble metal such asAu, Ag, Pd, Pt, Rh, Ru, Ir, Os and alloys thereof; alloys of Ni and P;alloys of Ni and Cr; alloys of Ni, Fe, and Co; W, and Ta. The ultra-thinseed layer may be comprised of a uniform alloy or composition, or may becomprised of a plurality of layers. For example, a capping layer mayalso be added to improve adhesion to photo resist layers deposited overthe seed layer. Under-layers or base layers may also be employed toimprove adhesion of the seed layer to the material underneath.Deposition of the ultra-thin seed layer 406 may be a uniform, blanketdeposition, or the deposition may be selectively limited to specificareas within each device die, and/or to regions surrounding theplurality of dies on the wafer. This may be done through additive (mask,deposit, remove mask) or subtractive (deposit, mask, etch, remove mask)processing. If a uniform, blanket deposition is used, the specificdevice structures to be electroplated within the die can be masked priorto plating, the additional unwanted ultra-thin seed layer being removedby etching subsequent to electroplating. One advantage of the presentinvention is that the very thin seed layers can be easily removedwithout damage to the subsequently plated structures. Although theultra-thin seed layer 406 is shown as a continuous layer in FIGS. 4 aand 4 b for simplicity of illustration, a selective deposition is alsosuitable, as is shown, for example, in FIG. 4 c.

FIG. 4 c is an expanded schematic plan view of die 404 c of FIG. 4 a, inaccordance with an embodiment of the present invention. In this expandedview, selective deposition of ultra-thin seed layers on previouslyfabricated active device regions 408 a, 408 b, 410 a, and 410 b areillustrated. The specific shapes of the active device regions areillustrative only, and not meant to limit this disclosure to or conveyany particular type of electronic device. Regions 408 a and 408 brepresent active devices wherein only a portion of the device area is tobe plated. Regions 410 a and 410 b represent regions where the entiredevice area is to be plated. Region 412 represents a structure where noelectroplating is desired. Device regions 408 a, 408 b, 410 a, 410 b areconnected to the perimeter region surrounding die 404 c by conductivepathways of ultra-thin seed layer 406. The actual deposition processwould involve numerous masking, deposition, and photo resist strippingsteps (not shown), which are well known to those skilled in the art. Aspreviously mentioned, the case of a blanket deposition of ultra-thinseed layer 406, wherein all structures within the die are uniformlycovered (not shown in FIG. 4 c), is also possible, and may be preferredto minimize seed layer resistance within the die 404 c. Following thedeposition of the ultra-thin seed layer, a thicker, conduction layer isvapor deposited on the wafer to reduce voltage drops from the outerperimeter of the wafer, where contact is made with the plating devicesand the wafer surface.

FIG. 5 a is a schematic plan view 500 of a wafer subsequent to the vapordeposition of conduction layer 502, in accordance with an embodiment ofthe present invention. FIG. 5 b is a cross sectional view 501 throughsection E-E of FIG. 5 a. Conduction layer 502 is considerably thickerand of lower resistance than ultra-thin seed layer 406. It need not beoptimized with respect to plated device structures, as its sole purposeis to facilitate plating current transport to regions surrounding (andin some cases extending into) the device die. As such, it is primarilydeposited in the outer perimeter regions of the wafer where electricalcontacts with the wafer are made during electroplating, and in thegalleys between the device die. In the perimeter areas surround eachdevice die, overlap between ultra-thin seed layer 406 and conductiveseed layer 502 must be provided to insure electrical conductivitybetween the two layers so that device areas covered by the ultra-thinseed layer 406 can be electroplated. Encroachment of conduction layer502 within the device die area may be permitted if it does not impededevice operation, or create problems requiring subsequent removal.Deposition of conduction layer 502 may be carried out by vapordeposition techniques, such as sputtering, CVD, evaporative deposition,e-beam deposition, and various plasma assisted deposition techniques.Deposition is limited to the areas shown by photo resist maskingtechniques, well known to those of ordinary skill in the art. Althoughprior art disclosures recommend electroplating of this layer,electroplating requires a seed layer prior to deposition. This seedlayer must effectively be much thicker than ultra-thin seed layer 406,requiring a second seed layer deposition prior to plating whenultra-thin seed layers are need to electroplate the device structures.Electroplating the conduction layer adds additional steps, which areeliminated by the present invention, using a vapor deposited conductionlayer.

Conduction layer 502 can be composed of any conductive material,preferably a metal or metal alloy, that can be deposited by a vapordeposition technique. All the materials and deposition techniques citedfor the ultra-thin seed layer are acceptable, with the inclusion of lowcost base metals such as copper and aluminum. Conduction layer 502 cancomprise a single layer, or have multiple layers. For example,conduction layer 502 could be composed of a copper or aluminum baselayer, covered with a thin gold protective layer, to reduce corrosion inthe plating bath. Conduction layer 502 must be compatible withultra-thin seed layer 406 with respect to adhesion, interfacialresistance, and galvanic corrosion. That is, the two layers (seed andconduction) must adhere to one another, there should be an acceptablylow resistance at their interface, and the coupling of the two layerscannot promote corrosion in the aqueous plating bath when the devicestructures are plated. Conduction layer 502 can range from about 20 nmto 100 nm in thickness, depending on its conductivity, with the moreconductive materials, such as copper and Rh, requiring thinner layers.

FIG. 5 c is an expanded schematic plan view of die 404 c of FIG. 5 a, inaccordance with an embodiment of the present invention. In this figure,the conduction layer 502 surrounds device die 404 c, providingconduction to selectively deposited regions on device structures 408 a,band 410 a,b. As disclosed above, a blanket deposition (not shown in FIG.5 c) of ultra-thin seed layer 406 may also be utilized.

FIGS. 6 a-7 c disclose an alternate embodiments of the presentinvention, wherein the deposition order of the conduction layer and theultra-thin seed layer(s) are reversed. FIG. 6 a is a schematic plan view600 of a wafer subsequent to the vapor deposition of conduction layer602. FIG. 6 b is a cross sectional view 601 through section F-F of FIG.6 a. In FIGS. 6 a and 6 b, conduction layer 602 is deposited on thewafer surface, primarily in the outer perimeter regions of the wafer andwithin the galleys between the device die, as was described forconduction layer 502 previously. FIG. 6 c is an expanded schematic planview of die 404 c of FIG. 6 a. In this figure, conduction layer 602 isexcluded from regions within die 404 c, although encroachment ofconduction layer 602 within the device die area may be permitted if itdoes not impede device operation, or create problems requiringsubsequent removal. Composition, thickness, and deposition techniquesdisclosed above for conduction layer 502 apply equally to conductionlayer 602.

FIG. 7 a is a schematic plan view 700 of a wafer subsequent to the vapordeposition of ultra-thin seed layer 702, in accordance with anembodiment of the present invention.

FIG. 7 b is a cross sectional view 701 through section G-G of FIG. 7 a.Ultra-thin seed layer 702 is deposited throughout the full wafersurface, covering layer 602. Deposition of the ultra-thin seed layer 702may be a uniform, blanket deposition, or the deposition may beselectively limited to specific areas within each device die, and/or toregions surrounding the plurality of dies on the wafer. This may be donethrough additive (mask, deposit, remove mask) or subtractive (deposit,mask, etch, remove mask) processing. If a uniform, blanket deposition isused, the specific structures to be electroplated within the die can bemasked prior to plating, the additional unwanted ultra-thin seed layerbeing removed by etching subsequent to electroplating. Ultra-thin seedlayer 702 is shown as a continuous layer in FIGS. 7 a and 7 b forsimplicity of illustration, a selective deposition is also suitable, asis shown, for example, in FIG. 7 c. Composition, thickness, anddeposition techniques disclosed above for ultra-thin seed layer 406apply equally to ultra-thin seed layer 702.

FIG. 7 c is an expanded schematic plan view of die 404 c of FIG. 7 a. Inthis expanded view, selective deposition of ultra-thin seed layers onactive device regions 408 a, 408 b, 410 a, and 410 b are illustrated.Regions 408 a and 408 b represent active devices wherein only a portionof the device area is to be plated. Regions 410 a and 410 b representregions where the entire device area is to be plated. Region 412represents a structure where no electroplating is desired. Deviceregions 408 a, 408 b, 410 a, 410 b are connected to the perimeter regionsurrounding die 404 c by conductive pathways of ultra-thin seed layer702. The actual deposition process would involve numerous masking,deposition, and photo resist stripping steps (not shown), which are wellknown to those skilled in the art. As previously mentioned, the case ofa blanket deposition of ultra-thin seed layer 702, wherein allstructures within the die are uniformly covered (not shown in FIG. 4 c),is also possible, and may be preferred to minimize seed layer resistancewithin the die 404 c.

FIG. 8 a is a schematic plan view 800 of a wafer subsequent to the vapordeposition of conduction layer 804, and the selective vapor depositionof a plurality of ultra-thin seed layers, in accordance with anembodiment of the present invention. FIG. 8 b is a cross sectional viewthrough section H-H of FIG. 8 a. FIGS. 8 a and 8 b disclose theselective vapor deposition of a plurality of ultra-thin seed layers 802a-802 f following the vapor deposition of conductive layer 804. Ofcourse, as will be recognized by those skilled in the art, thedeposition order can also be reversed, wherein the plurality ofultra-thin seed layers is deposited on the wafer prior to the depositionof conductive layer 804. The plurality of ultra-thin seed layers can bedistinguished from one another by thickness, composition, or both.Although FIGS. 8 a and 8 b indicate that the same ultra-thin seed layeris used within a particular vertical column of die, it will be evidentto those skilled in the art that any combination of ultra-thin seedlayer parameters can be employed in any die, in random fashion.Deposition of the ultra-thin seed layers 802 a-802 f may be a uniformdeposition within each die, or the deposition may be selectively limitedto specific areas within each device die. This may be done throughadditive (mask, deposit, remove mask) or subtractive (deposit, mask,etch, remove mask) processing. Composition, thickness, and depositiontechniques disclosed above for ultra-thin seed layer 406 apply equallyto ultra-thin seed layers 802 a-802 f. Composition, thickness, anddeposition techniques disclosed above for conduction layer 502 applyequally to conduction layer 802.

FIG. 8 c is an expanded schematic plan view of die 404 c of FIG. 8 a. Inthis figure, for example, various ultra-thin compositions and/orthicknesses are applied to different device structures 408 a′, 408 b′,410 a′, 410 b′, 410 c′ within die 404 c. Each may be electroplated withdifferent materials, in separate stages, if required. Conduction pathsare provided from each device area to the surrounding conduction film804. The actual deposition process would involve numerous masking,deposition, and photo resist stripping steps (not shown), which are wellknown to those skilled in the art.

FIG. 9 a is a schematic block diagram of a first electroplating process900, in accordance with an embodiment of the present invention. In step902, ultra-thin seed layers are vapor deposited in the wafer surface, inaccordance with the processes and limitations previously disclosed. Instep 904, the conduction layer is deposited, also in accordance with theprocesses and limitations previously disclosed. In step 906, a platingmask is deposited to limit the plating deposition to desired areas andstructures within the device die, using processes well known to thoseskilled in the art. In step 908, the device structures areelectroplated. In an optional step (not shown), the ultra-thin seedlayers can be removed by etching without damage to remaining structures.

FIG. 9 b is a schematic block diagram of a second electroplating process901, in accordance with an embodiment of the present invention. In thisprocess, steps 902 and 904 are reversed.

FIG. 9 c is a schematic block diagram of process step 902 of FIGS. 9 aand 9 b, in accordance with an embodiment of the present invention. Thisgeneralized process illustrates the deposition of more than oneultra-thin seed layer in electroplating processes 900 and 901. In step910, a first Mask₁ is deposited. In step 912, a first ultra-thin seedlayer UTSL₁ is selectively vapor deposited. In step 914, Mask₁ isremoved, leaving a portion of UTSL₁ on the wafer surface. Steps 916-926are optional, depending on the number of seed layers to be deposited. Instep 916, a second Mask₂ is deposited. In step 918, a first ultra-thinseed layer UTSL₂ is selectively vapor deposited. In step 920, Mask₂ isremoved, leaving a portion of UTSL₂ on the wafer surface. The processcontinues until the last (Mask_(n) and UTSL_(n)) are deposited, in steps922-926.

FIG. 9 d is a schematic block diagram of process step 904 of FIGS. 9 aand 9 b, in accordance with an embodiment of the present invention. Instep 930, a mask for the conduction layer is deposited, which limitsdeposition of the conduction layer to the desired areas on the wafer. Instep 932, the conduction layer is vapor deposited, in accordance withthe processes and limitations previously disclosed. In step 934, themask is removed.

The present invention is not limited by the previous embodimentsheretofore described. Rather, the scope of the present invention is tobe defined by these descriptions taken together with the attached claimsand their equivalents.

1. A method for electroplating device structures, comprising: vapordepositing a first seed layer on a first portion of a wafer surface;vapor depositing a second seed layer on a second portion of said wafersurface; vapor depositing a conduction layer on a third portion of saidwafer surface, wherein said conduction layer is electrically coupled tosaid first and said second seed layers; electroplating a first devicestructure on said first seed layer by conducting electrical currentthrough said conduction layer to said first seed layer; and,electroplating a second device structure on said second seed layer byconducting electrical current through said conduction layer to saidsecond seed layer.
 2. The method as recited in claim 1, wherein saidfirst seed layer and said second seed layer are less than 25 nm thick.3. The method as recited in claim 2, wherein said first seed layer andsaid second seed layer comprise different materials.
 4. The method asrecited in claim 2, wherein said first seed layer and said second seedlayer comprise a noble metal.
 5. The method as recited in claim 2,wherein said first seed layer and said second seed layer comprise atleast one of Ni, Fe, Co, and Cr.
 6. The method as recited in claim 2,wherein said first seed layer and said second seed layer comprise Ta. 7.The method as recited in claim 2, wherein said first seed layer and saidsecond seed layer comprise a plurality of layers.
 8. The method asrecited in claim 1, wherein said conduction layer is greater than 20 nmin thickness.
 9. The method as recited in claim 8, wherein saidconduction layer comprises a noble metal.
 10. The method as recited inclaim 8, wherein said conduction layer comprises at least one of Cu andAl.
 11. The method as recited in claim 8, wherein said conduction layercomprises a plurality of layers.
 12. The method as recited in claim 1,wherein vapor deposition of said conduction layer comprises sputteringsaid conduction layer.
 13. A method for electroplating devicestructures, comprising: vapor depositing a conduction layer on a firstportion of a wafer surface; vapor depositing a seed layer on a secondportion of said wafer surface, and on at least a portion of saidconduction layer; and, electroplating a device structure on said seedlayer covering said second portion of said wafer surface, by conductingelectrical current through said conduction layer to at least a portionof said seed layer.
 14. The method as recited in claim 13, wherein saidseed layer is less than 25 nm thick.
 15. The method as recited in claim14, wherein said seed layer comprises a noble metal.
 16. The method asrecited in claim 14, wherein said seed layer comprises at least one ofNi, Fe, Co, and Cr.
 17. The method as recited in claim 14, wherein saidseed layer comprises Ta.
 18. The method as recited in claim 14, whereinsaid seed layer comprises a plurality of layers.
 19. The method asrecited in claim 13, wherein said conduction layer is greater than 20 nmin thickness.
 20. The method as recited in claim 19, wherein saidconduction layer comprises a noble metal.
 21. The method as recited inclaim 19, wherein said conduction layer comprises at least one of Cu andAl.
 22. The method as recited in claim 19, wherein said conduction layercomprises a plurality of layers.
 23. The method as recited in claim 13,wherein vapor deposition of said conduction layer comprises sputteringsaid conduction layer.